Semiconductor IP verification engineer

[V/B]

Капиталистические эксплуататоры из компании Synopsys ищут дополнительных работников. Если Вам интересны позиции описанные ниже, Вы можете послать Ваше резюме мне (подробности через ЛС) и я его пошлю кому надо. Также Вы можете подать Ваше резюме через сайт компании.

Работа в Дублине 15 (Бланч). Work Permit / Green Card сделают для подходящего кандидата.

Verification Engineer
We are seeking self-driven chip design and verification engineers to join our highly successful team. The successful candidates will contribute to the development of these complex IP blocks, working at all levels, concept, architectural definition, block specification, design, implementation and verification.
Requirements:
• Previous experience in advanced verification methodologies (RVM/OVM/VMM) would be beneficial
• 4+ years design/verification experience
• Knowledge of SystemVerilog/OOP/PCIe would be beneficial
• Exposure to Verilog/VHDL
• Good problem solving and communication skills

R&D Engineer, II
In this position the successful candidate will work within the DDR Controller IP group and will be responsible for designing, developing, and verifying semiconductor IP. The role involves development of RTL, verification testbenches, tests, as well as development of utilities and scripts as required.

Requirements:
Experience in design and development of RTL using Verilog high level development language is required. Experience in the development of verification testbenches using System Verilog is or advanced verification methodologies such as VMM is also required. Prior knowledge and experience of DDR memory systems is an advantage.
The successful candidate shall demonstrate strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills.
This position typically requires a relevant university degree with a minimum of 2 years related experience.